In Patent Document 1, there is disclosed a voltage conversion circuit (regulator) including a differential amplifier with a push-pull output structure of a current mirror configuration. In order to describe the voltage conversion circuit in Patent Document 1, FIG. 10 is created based on FIG. 1 of Patent Document 1. Referring to FIG. 10, the voltage conversion circuit includes an error amplifier that is configured as a differential amplifier and that outputs error amplification output to a node N1, and a buffer circuit that receives the output from the error amplifier and outputs an output voltage Vout3 to a node N2. The differential amplifier as the error amplifier includes a differential input stage and a push-pull type output unit of a current mirror circuit configuration.
In more detail, referring to FIG. 10, the differential input stage of the differential amplifier includes:
an n-channel MOS transistor (current source transistor) Q9 that has a source connected to GND (ground) and has a gate to which a bias voltage BN I supplied;
a differential pair including:
n-channel MOS transistors Q1 and Q2 that have sources coupled together and connected to a drain of the current source transistor Q9; and
diode-connected p-channel MOS transistors Q3 and Q5 that have sources connected in common to a power supply terminal VDD, and have drains respectively connected to drains of the transistors Q1 and Q2.
The differential amplifier output portion (push-pull type output portion of the current mirror circuit configuration) includes:
a p-channel MOS transistor Q4 that has a source connected to the power supply terminal VDD and has a gate connected to a gate of the p-channel MOS transistor Q3;
a p-channel MOS transistor Q6 that has a source connected to the power supply terminal VDD and has a gate connected to a gate of the p-channel MOS transistor Q5;
an n-channel MOS transistor Q7 that has a source connected to ground and has a drain and a gate connected to a drain of the p-channel MOS transistor Q4; and
an n-channel MOS transistor Q8 that has a source connected to GND, has a gate connected to a gate of the n-channel MOS transistor Q7, and has a drain connected to a drain of the transistor Q6. The transistors Q8 and Q6 compose push-pull transistors. The p-channel MOS transistors Q3 and Q4 compose a first current mirror circuit, the p-channel MOS transistors Q5 and Q6 compose a second current mirror circuit, and the n-channel MOS transistors Q7 and Q8 form a compose third current mirror circuit.
A reference voltage Vref is supplied from a reference voltage generation circuit (not shown), to the gate of the n-channel MOS transistor Q1 constituting the differential pair, and an output Vout3 of the buffer circuit is fed back to a gate of the n-channel MOS transistor Q2. The bias voltage BN (denoted as F1 in Patent Document 1) is supplied from a bias circuit (not shown) to a gate of the current source transistor Q9.
The buffer circuit includes:
a p-channel MOS transistor (drive transistor) Q10 that has a source connected to a power supply terminal VDD, has a gate connected to a node N1 (output of differential amplifier output portion), and has a drain connected to a node N2 (regulator output); and
a resistance element R1 between the node N2 and GND. In Patent Document 1, the resistance element R1 between the node N2 and GND includes an n-channel MOS transistor (not shown in FIG. 10) that has a source connected to GND, has a drain connected to the node N2, and has a gate to which a bias voltage is supplied. This n-channel MOS transistor is arranged such that a current source is configured so that a current (idling current) of an appropriate amount flows in the drive transistor Q10 even when a load current I3 becomes particularly small.
The drive transistor Q10 is in an operation state so as to have an appropriate gain, irrespective of large amount of change in the load current I3 due to this idling current. In Patent Document 1, there is provided a p-channel MOS transistor (control transistor) (not shown in FIG. 10) that has a source connected to the power supply terminal VDD, has a gate connected to a bias voltage, and has a drain connected to the node N1. This control transistor is provided so that, by switch-controlling the gate bias voltage BN (F1 in Patent Document 1) of the current source transistor Q9 to 0V, when operation of the voltage conversion circuit is stopped, synchronization thereto is performed, and the drive transistor Q10 is preferably cut off.
In the configuration of FIG. 10, the amount of current flowing to the push-pull type output portion transistors Q6 and Q8, is adjusted by the differential input stage and the current mirror circuit and the gate potential of the drive transistor Q10 is able to be lowered to almost a GND potential. It is possible to increase gate-to-source voltage of the drive transistor Q10, and to increase drive capability of the buffer circuit (drive transistor Q10).
[Patent Document 1]
    JP Patent Kokai Publication No. JP-A-10-64261